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december 2007 rev 4 1/69 1 m28w320fct m28w320fcb 32 mbit (2mb x16, boot block) 3v supply flash memory features supply voltage ?v dd = 2.7v to 3.6v core power supply ?v ddq = 1.65v to 3.6v for input/output ?v pp = 12v for fast program (optional) access time: 70, 80, 90, 100ns programming time ? 10s typical ? double word programming option ? quadruple word programming option common flash interface memory blocks ? parameter blocks (top or bottom location) ? main blocks block locking ? all blocks locked at power up ? any combination of blocks can be locked ?wp for block lock-down security ? 128 bit user programmable otp cells ? 64 bit unique device identifier automatic stand-by mode program and erase suspend 100,000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? top device code, m28w320fct: 88bah ? bottom device code, m28w320fcb: 88bbh ecopack ? packages tsop48 (n) 12 x 20mm fbga tfbga47 (zb) 6.39 x 6.37mm www.numonyx.com
contents m28w320fct, m28w320fcb 2/69 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 address inputs (a0-a20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 output enable (g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 reset (rp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m28w320fct, m28w320fcb contents 3/69 4.9 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.11 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.15 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 26 6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5 v pp status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix b common flash interface (c fi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
contents m28w320fct, m28w320fcb 4/69 appendix c flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 appendix d command interface and program/era se controller state . . . . . . . 64 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
m28w320fct, m28w320fcb list of tables 5/69 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. read block lock signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. read protection register and lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. program, erase times and program/erase endurance cycles . . . . . . . . . . . . . . . . . . . . . 24 table 9. block lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. write ac characteristics, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. power-up and reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . . . 41 table 21. tfbga47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, package mechanical data . . . . . 42 table 22. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. top boot block addresses, m28w320fct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. bottom boot block addresses, m28w320fcb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 27. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 29. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. primary algorithm-specific extended query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 31. security code area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 32. write state machine current/next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 33. write state machine current/next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 34. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
list of figures m28w320fct, m28w320fcb 6/69 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. power-up and reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . . . . 41 figure 13. tfbga47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, bottom view package outline . . 42 figure 14. tfbga47 daisy chain - package connections (top view through package) . . . . . . . . . . 43 figure 15. tfbga47 daisy chain - pcb connections pr oposal (top view through package) . . . . . . 43 figure 16. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 17. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 18. quadruple word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 19. program suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 figure 21. erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 22. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 23. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 63
m28w320fct, m28w320fcb summary description 7/69 1 summary description the m28w320fct and m28w320fcb are 32 mbit (2 mbit x 16) non-volatile flash memories that can be erased electrically at the block level and programmed in-system on a word-by-word basis. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. v ddq allows to drive the i/o pin down to 1.65v. an optional 12v v pp power supply is provided to speed up customer programming. the devices feature an asymmetrical blocked architecture. they have an array of 71 blocks: 8 parameter blocks of 4 kword and 63 main blocks of 32 kword. m28w320fct has the parameter blocks at the top of the memory address space while the m28w320fcb locates the parameter blocks starting from the bottom. the memory maps are shown in figure 4: block addresses . both devices feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power up. each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. the device includes a protection register to increase the protection of a system design. the protection register is divided into two segm ents, the first is a 64 bit area which contains a unique device number written by numonyx, while the second is a 128 bit area, one-time- programmable by the user. the user programmable segment can be permanently protected. figure 5 , shows the protection register memory map. program and erase commands are written to the command interface of the memory. an on- chip program/erase controller takes care of the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the memory is offered in tsop48 (10 x 20mm) and tfbga47 (6.39 x 6.37mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ?1?). in order to meet environmental requirements, numonyx offers the m28w320fct and m28w320fcb in ecopack ? packages.ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label.
summary description m28w320fct, m28w320fcb 8/69 figure 1. logic diagram table 1. signal names a0-a20 address inputs dq0-dq15 data input/output e chip enable g output enable w write enable rp reset wp write protect v dd core power supply v ddq power supply for input/output v pp optional supply voltage for fast program & erase v ss ground nc not connected internally ai09900 21 a0-a20 w dq0-dq15 v dd m28w320fct m28w320fcb e v ss 16 g rp wp v ddq v pp
m28w320fct, m28w320fcb summary description 9/69 figure 2. tsop connections dq3 dq9 dq2 a6 dq0 w a3 nc dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai09901b m28w320fct m28w320fcb 12 1 13 24 25 36 37 48 dq8 a20 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ssq
summary description m28w320fct, m28w320fcb 10/69 figure 3. tfbga connections (top view through package) ai03847b c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ssq dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp a19 a20
m28w320fct, m28w320fcb summary description 11/69 figure 4. block addresses 1. also see appendix a , table 24 and table 25 for a full listing of the block addresses. figure 5. protection register memory map ai09902 4 kwords 1fffff 1ff000 32 kwords 00ffff 008000 32 kwords 007fff 000000 m28w320fct top boot block addresses 4 kwords 1f8fff 1f8000 32 kwords 1f0000 1f7fff total of 8 4 kword blocks total of 63 32 kword blocks 4 kwords 1fffff 1f8000 32 kwords 32 kwords 000fff 000000 m28w320fcb bottom boot block addresses 4 kwords 1f7fff 00ffff 32 kwords 1f0000 008000 total of 63 32 kword blo c total of 8 4 kword bloc k 007fff 007000 ai05520 user programmable otp unique device number protection register lock 2 (1) 10 8ch 85h 84h 81h 80h protection register note1. bit 2 of the protection register lock must not be programmed to 0.
signal descriptions m28w320fct, m28w320fcb 12/69 2 signal descriptions see figure 1: logic diagram and figure 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a20) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 data input/output (dq0-dq15) the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. 2.4 output enable (g ) the output enable controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable, e, or write enable, w , whichever occurs first. 2.6 write protect (wp ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the block cannot be changed. when write protect is at v ih , the lock-down is disabled and the block can be locked or unlocked. (refer to table 7: read protection register and lock register ). 2.7 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is
m28w320fct, m28w320fcb signal descriptions 13/69 minimized. after reset all blocks are in the locked state. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters read array mode, but a negative transition of chip enable or a change of the address is required to ensure valid data outputs. 2.8 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.9 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. 2.10 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. the supply voltage v dd and the program supply voltage v pp can be applied in any order. if v pp is kept in a low voltage range (0v to 3.6v) v pp is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 enables these functions (see table 15: dc characteristics ). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on program or erase, however for double or quadruple word program the results are uncertain. if v pp is in the range 11.4v to 12.6v it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed (see ta bl e 1 7 and ta b l e 1 8 ). 2.11 v ss ground v ss is the reference for all voltage measurements. note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f capacitor close to the pin. see figure 7: ac measurement load circuit . the pcb trace widths should be sufficient to carry the required v pp program and erase currents.
bus operations m28w320fct, m28w320fcb 14/69 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, output disable, standby, automatic standby and reset. see ta b l e 2 : b u s operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 read read bus operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figure 8: read ac waveforms , and table 16: read ac characteristics , for details of when the output becomes valid. read mode is the default state of the device when exiting reset or after power-up. 3.2 write bus write operations write commands to the memory or latch input data to be programmed. a write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. see figure 9 and figure 10 , write ac waveforms, and ta b l e 1 7 and ta bl e 1 8 , write ac characteristics, for details of the timing requirements. 3.3 output disable the data outputs are high impedance when the output enable is at v ih . 3.4 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in stand-by when chip enable is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished.
m28w320fct, m28w320fcb bus operations 15/69 3.5 automatic standby automatic standby provides a low power consumption state during read mode. following a read operation, the device enters automatic standby after 150ns of bus inactivity even if chip enable is low, v il , and the supply current is reduced to i dd1 . the data inputs/outputs will still output data if a bus read operation is in progress. 3.6 reset during reset mode when output enable is low, v il , the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 2. bus operations (1) operation e g w rp wp v pp dq0-dq15 bus read v il v il v ih v ih x don't care data output bus write v il v ih v il v ih xv dd or v pph data input output disable v il v ih v ih v ih x don't care hi-z standby v ih xxv ih x don't care hi-z reset x x x v il x don't care hi-z 1. x = v il or v ih , v pph = 12v 5%.
command interface m28w320fct, m28w320fcb 16/69 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time during, to monitor the progress of the operation, or the program/erase states. see table 3: command codes , for a summary of the commands and see appendix d , and ta b l e 3 2 , write state machine current/next, for a summary of the command interface. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands w ill reset the device to read mode. refer to table 4: commands , in conjunction with the text descriptions below. 4.1 read memory array command the read command returns the memory to it s read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. subsequent read o perations will read the addressed loca tion and output the data. when a device reset occurs, the memory defaults to read mode. 4.2 read status register command the status register indicates when a program or erase operation is complete and the success or failure of the operation itself. issue a read status register command to read the status register?s contents. subsequent bus read operations read the status register at any address, until another command is issued. see table 11: status register bits , for details on the definitions of the bits. the read status register command may be issued at any time, even during a program/erase operation. any read attemp t during a program/erase operation will automatically output the content of the status register.
m28w320fct, m28w320fcb command interface 17/69 4.3 read electronic signature command the read electronic signature command reads the manufacturer and device codes and the block locking status, or the protection register. the read electronic signat ure command consists of one writ e cycle, a subsequent read will output the manufacturer code, the device code, the block lock and lock-down status, or the protection and lock register. see ta b l e 5 , ta b l e 6 and ta b l e 7 for the valid address. 4.4 read cfi query command the read query command is used to read data from the common flash interface (cfi) memory area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device . one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash interface memory area. see appendix b: common flash interface (cfi) , ta bl e 2 6 , ta b l e 2 7 , ta bl e 2 8 , ta b l e 2 9 , ta b l e 3 0 and ta bl e 3 1 for details on the information contained in the common flash interface memory area. table 3. command codes hex code command 01h block lock confirm 10h program 20h erase 2fh block lock-down confirm 30h double word program 40h program 50h clear status register 55h reserved 56h quadruple word program 60h block lock, block unlock, block lock-down 70h read status register 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block unlock confirm ffh read memory array
command interface m28w320fct, m28w320fcb 18/69 4.5 block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. 1. the first bus cycle sets up the erase command. 2. the second latches the block address in the internal state machine and starts the program/erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. during erase operations the memory will acce pt the read status register command and the program/erase suspend comm and, all other commands will be ignored. typical erase times are given in table 8: program, erase times and program/erase endurance cycles . see appendix c , figure 20: erase flowchart and pseudo code , for a suggested flowchart for using the erase command. 4.6 program command the memory array can be programmed word-by-word. two bus write cycles are required to issue the program command. 1. the first bus cycle sets up the program command. 2. the second latches the address and the data to be written and starts the program/erase controller. during program operations the memory will acc ept the read st atus register command and the program/erase suspend command. typical program times are given in ta bl e 8 : program, erase times and program/erase endurance cycles . programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c , figure 16: program flowchart and pseudo code , for the flowchart for using the program command.
m28w320fct, m28w320fcb command interface 19/69 4.7 double word program command this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.the two words must differ only for the address a0. programming should not be attempted when v pp is not at v pph . three bus write cycles are necessary to issue the double word program command. 1. the first bus cycle sets up the double word program command. 2. the second bus cycle latches the address and the data of the first word to be written. 3. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations output the status register content after the programming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c , figure 17: double word program flowchart and pseudo code , for the flowchart for using the double word program command. 4.8 quadruple word program command this feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.the four words must differ only for the addresses a0 and a1. programming should not be attempted when v pp is not at v pph . five bus write cycles are necessary to is sue the quadruple word program command. 1. the first bus cycle sets up the quadruple word program command. 2. the second bus cycle latches the address and the data of the first word to be written. 3. the third bus cycle latches the address and the data of the second word to be written. 4. the fourth bus cycle latches the address and the data of the third word to be written. 5. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations output the status register content after the programming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c , figure 18: quadruple word program flowchart and pseudo code , for the flowchart for using the quadruple word program command. 4.9 clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to ?0?. one bus write cycle is required to issue the clear status register command. the bits in the status register do not automatically return to ?0? when a new program or erase command is issued. the error bits in the status register should be cleared before attempting a new program or erase command.
command interface m28w320fct, m28w320fcb 20/69 4.10 program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. one bus write cycle is required to issue the program/erase command and pause the program/erase controller. during program/erase suspend the command interface will accept the program/erase resume, read array, read status register, read electronic signature and read cfi query commands. additionally, if the suspend operation was erase then the program, double word program, quadruple word program, block lock, block lock-down or protection program commands will also be accepted. the block being erased may be protected by issuing the block protect, block lock or protection program commands. when the program/erase resume comm and is issued the operation will complete. only the blocks not being erased may be read or programmed correctly. during a program/erase suspend, the device can be placed in a pseudo-standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c , figure 19: program suspend & resume flowchart and pseudo code , and figure 21: erase suspend & resume flowchart and pseudo code for flowcharts for using the program/erase suspend command. 4.11 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the command. once the command is issued subsequent bus read operations read the status register. see appendix c , figure 19: program suspend & resume flowchart and pseudo code , and figure 21: erase suspend & resume flowchart and pseudo code , and figure 21: erase suspend & resume flowchart and pseudo code for flowcharts for using the program/erase resume command. 4.12 protection register program command the protection register program command is used to program the 128 bit user one-time- programmable (otp) segment of the protection register. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two write cycles are required to issue the protection register program command. 1. the first bus cycle sets up the pr otection register program command. 2. the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register content after the programming has started. the segment can be protected by programming bit 1 of the protection lock register (see figure 5: protection register memory map ). attempting to program a previously protected protection register will re sult in a status register error. the protection of the protection register is not reversible. the protection register program cannot be suspended.
m28w320fct, m28w320fcb command interface 21/69 4.13 block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. 1. the first bus cycle sets up the block lock command. 2. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 0 shows the protection status after issuing a block lock command. the block lock bits are volatile, once set they remain set until a hardware reset or power- down/power-up. they are cleared by a blocks unlock command. refer to the section, block locking, for a detailed explanation. 4.14 block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command. 1. the first bus cycle sets up the block unlock command. 2. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 0 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation. 4.15 block lock-down command a locked block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. 1. the first bus cycle sets up the block lock command. 2. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 1 0 shows the protection status after issuing a block lock-down command. refer to the section, block locking, for a detailed explanation.
command interface m28w320fct, m28w320fcb 22/69 table 4. commands (1)(2) commands cycles bus write operations 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle op add data op add data op add data op add data op add data read memory array 1+ write x ffh read ra rd read status register 1+ write x 70h read x srd read electronic signature 1+ write x 90h read sa (3) idh read cfi query 1+ write x 98h read qa qd erase 2 write x 20h write ba d0h program 2 write x 40h or 10h write pa pd double word program (4) 3 write x 30h write pa1 pd1 write pa2 pd2 quadruple word program (5) 5write x 56h (6) w r i t e pa 1 p d 1 w r i t e pa 2 p d 2 w r i t e pa 3 p d 3 w r i t e pa 4 p d 4 clear status register 1 write x 50h program/erase suspend 1write x b0h program/erase resume 1write x d0h block lock 2 write x 60h write ba 01h block unlock 2 write x 60h write ba d0h block lock-down 2 write x 60h write ba 2fh protection register program 2write x c0hwritepraprd 1. x = don't care, ra=read address, rd=read data, srd=status register data, id=identifier (manufacture and device code), qa=query address, qd=quer y data, ba=block address, pa=program address, pd=program data, pra=protection register address, prd=protection register data. 2. 55h is reserved. 3. the signature addresses are listed in table 5 , table 6 and table 7 . 4. program addresses 1 and 2 must be consec utive addresses differing only for a0. 5. program addresses 1,2,3 and 4 must be cons ecutive addresses diffe ring only for a0 and a1. 6. to be characterized.
m28w320fct, m28w320fcb command interface 23/69 table 5. read electronic signature (1) code device e g w a0 a1 a2-a7 a8-a20 dq0-dq7 dq8-dq15 manufacture. code v il v il v ih v il v il 0 don't care 20h 00h device code m28w320fct v il v il v ih v ih v il 0 don't care bah 88h m28w320fcb v il v il v ih v ih v il 0 don't care bbh 88h 1. rp = v ih . table 6. read block lock signature block status e g w a0 a1 a2-a7 a8-a11 a12-a20 dq0 dq1 dq2-dq15 locked block v il v il v ih v il v ih 0 don't care block address 1 0 00h unlocked block v il v il v ih v il v ih 0 don't care block address 0 0 00h locked-down block v il v il v ih v il v ih 0 don't care block address x (1) 100h 1. a locked-down block can be locked "dq0 = 1" or unlocked "dq0 = 0"; see block locking section. table 7. read protection register and lock register word e g w a0- a7 a8-a20 dq0 dq1 dq2 dq3- dq7 dq8- dq15 lock v il v il v ih 80h don't care don't care otp prot. data don't care see note (1) don't care don't care unique id 0 v il v il v ih 81h don't care id data id data id data id data id data unique id 1 v il v il v ih 82h don't care id data id data id data id data id data unique id 2 v il v il v ih 83h don't care id data id data id data id data id data unique id 3 v il v il v ih 84h don't care id data id data id data id data id data otp 0 v il v il v ih 85h don't care otp data otp data otp data otp data otp data otp 1 v il v il v ih 86h don't care otp data otp data otp data otp data otp data otp 2 v il v il v ih 87h don't care otp data otp data otp data otp data otp data otp 3 v il v il v ih 88h don't care otp data otp data otp data otp data otp data otp 4 v il v il v ih 89h don't care otp data otp data otp data otp data otp data otp 5 v il v il v ih 8ah don't care otp data otp data otp data otp data otp data otp 6 v il v il v ih 8bh don't care otp data otp data otp data otp data otp data otp 7 v il v il v ih 8ch don't care otp data otp data otp data otp data otp data 1. dq2 in the protection lock register must not be programmed to 0.
command interface m28w320fct, m28w320fcb 24/69 table 8. program, erase times and program/erase endurance cycles parameter test conditions m28w320fct, m28w320fcb unit min typ max word program v pp = v dd 10 200 s double word program v pp = 12v 5% 10 200 s quadruple word program v pp = 12v 5% 10 200 s main block program v pp = 12v 5% 0.16/0.08 (1) 5s v pp = v dd 0.32 5 s parameter block program v pp = 12v 5% 0.02/0.01 (1) 4s v pp = v dd 0.04 4 s main block erase v pp = 12v 5% 1 10 s v pp = v dd 110s parameter block erase v pp = 12v 5% 0.4 10 s v pp = v dd 0.4 10 s program/erase cycles (per block) 100,000 cycles data retention 20 years 1. typical time to program a main or parameter block using the double wo rd program and the quadruple word program commands respectively.
m28w320fct, m28w320fcb block locking 25/69 5 block locking the m28w320fct and m28w320fcb feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software-only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and lock-down. table 10 defines all of the possible protection states (wp , dq1, dq0), and appendix c , figure 22 , shows a flowchart for the locking operations. 5.1 reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subsequent reads at the address specified in ta bl e 6 , will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. 5.2 locked state the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase operations attempted on a lo cked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. 5.3 unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by issuing the unlock command.
block locking m28w320fct, m28w320fcb 26/69 5.4 lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,1) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be locked again (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low, blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks, including those in lock-down, to the locked state. 5.5 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or pr ogram operations, resume the erase operation with the erase resume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix d: command interface and program/erase controller state , for detailed information on which commands are valid during erase suspend. table 9. block lock status item address data block lock configuration xx002 lock block is unlocked dq0=0 block is locked dq0=1 block is locked-down dq1=1
m28w320fct, m28w320fcb block locking 27/69 table 10. protection status current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) 1. the lock status is defined by the write protect pin and by dq 1 (?1? for a locked-down block) and dq0 (?1? for a locked block) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the pr evious dq0 value, giving a 111 or 110.
status register m28w320fct, m28w320fcb 28/69 6 status register the status register provides information on the current or previous program or erase operation. the various bits convey information and errors on the operation. to read the status register the read status register command can be issued, refer to read status register command section. to output the contents, the status register is latched on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . either chip enable or output enable must be toggled to update the latched data. bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 11: status register bits . refer to ta bl e 1 1 in conjunction with the following text descriptions. 6.1 program/erase controller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is high. during program, erase, operations the program/erase controller status bit can be polled to find the end of the operation. other bits in the status register should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. 6.2 erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended or is going to be suspended. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status should only be considered valid when the program/erase controller status bit is high (program/erase c ontroller inactive). bit 7 is set within 30s of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
m28w320fct, m28w320fcb status register 29/69 6.3 erase status (bit 5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to ?1?), the program/erase controller has applied th e maximum number of pulses to the block and still failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 6.4 program status (bit 4) the program status bit is used to identify a program failure. when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the byte and still failed to ve rify that it has programmed co rrectly. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. 6.5 v pp status (bit 3) the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can occur if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 6.6 program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended. when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). bit 2 is set within 5s of the program/erase suspend command being issued therefore the memory may still complete the operation rat her than entering the suspend mode. when a program/erase resume command is issued the program suspend status bit returns low.
status register m28w320fct, m28w320fcb 30/69 6.7 block protection status (bit 1) the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to ?1?), a program or erase operation has been attempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new command is issued, otherwise t he new command will appear to fail. 6.8 reserved (bit 0) bit 0 of the status register is reserved. its value must be masked. note: refer to appendix c: flowcharts and pseudo codes , for using the status register. table 11. status register bits bit name logic level (1) definition 7 p/e.c. status '1' ready '0' busy 6 erase suspend status '1' suspended '0' in progress or completed 5 erase status '1' erase error '0' erase success 4 program status '1' program error '0' program success 3v pp status '1' v pp invalid, abort '0' v pp ok 2 program suspend status '1' suspended '0' in progress or completed 1 block protection status '1' program/erase on protected block, abort '0' no operation to protected blocks 0 reserved 1. logic level '1' is high, '0' is low.
m28w320fct, m28w320fcb maximum rating 31/69 7 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 12. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature (1) 1. depends on range. ? 40 85 c t bias temperature under bias ? 40 125 c t stg storage temperature ? 55 155 c v io input or output voltage ? 0.6 v ddq +0.6 v v dd , v ddq supply voltage ? 0.6 4.1 v v pp program voltage ? 0.6 13 v
dc and ac parameters m28w320fct, m28w320fcb 32/69 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e : . designers should check that the operatin g conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 6. ac measurement i/o waveform table 13. operating and ac measurement conditions parameter m28w320fct, m28w320fcb 70 85 90 10 units min max min max min max min max v dd supply voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 v v ddq supply voltage (v ddq v dd ) 2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 v ambient operating temperature ? 40 85 ? 40 85 ? 40 85 ? 40 85 c load capacitance (c l )50 50 50 50pf input rise and fall times 5 5 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ai00610 v ddq 0v v ddq /2
m28w320fct, m28w320fcb dc and ac parameters 33/69 figure 7. ac measurement load circuit ai00609c v ddq c l c l includes jig capacitance 25k device under test 0.1f v dd 0.1f v ddq 25k table 14. capacitance (1) symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf 1. sampled only, not 100% tested. table 15. dc characteristics symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 10 a i dd supply current (read) e = v ss , g = v ih , f = 5mhz 9 18 ma i dd1 supply current (stand-by or automatic stand-by) e = v ddq 0.2v, rp = v ddq 0.2v 15 50 a i dd2 supply current (reset) rp = v ss 0.2v 15 50 a i dd3 supply current (program) program in progress v pp = 12v 5% 510ma program in progress v pp = v dd 10 20 ma i dd4 supply current (erase) erase in progress v pp = 12v 5% 520ma erase in progress v pp = v dd 10 20 ma i dd5 supply current (program/erase suspend) e = v ddq 0.2v, erase suspended 15 50 a i pp program current (read or stand-by) v pp > v dd 400 a
dc and ac parameters m28w320fct, m28w320fcb 34/69 i pp1 program current (read or stand-by) v pp v dd 15a i pp2 program current (reset) rp = v ss 0.2v 1 5 a i pp3 program current (program) program in progress v pp = 12v 5% 110ma program in progress v pp = v dd 15a i pp4 program current (erase) erase in progress v pp = 12v 5% 310ma erase in progress v pp = v dd 15a v il input low voltage ?0.5 0.4 v v ddq 2.7v ?0.5 0.8 v v ih input high voltage v ddq ?0.4 v ddq +0.4 v v ddq 2.7v 0.7 v ddq v ddq +0.4 v v ol output low voltage i ol = 100a, v dd = v dd min, v ddq = v ddq min 0.1 v v oh output high voltage i oh = ?100a, v dd = v dd min, v ddq = v ddq min v ddq ?0.1 v v pp1 program voltage (program or erase operations) 1.65 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v pplk program voltage (program and erase lock- out) 1v v lko v dd supply voltage (program and erase lock- out) 2v table 15. dc characteristics (continued) symbol parameter test condition min typ max unit
m28w320fct, m28w320fcb dc and ac parameters 35/69 figure 8. read ac waveforms dq0-dq15 ai02688b valid a0-a20 e taxqx tavav valid tavqv telqv telqx tglqv tglqx addr. valid chip enable outputs enabled data valid standby g tghqx tghqz tehqx tehqz table 16. read ac characteristics symbol alt parameter m28w320fct, m28w320fcb unit 70 85 90 10 t avav t rc address valid to next address valid min 70 85 90 100 ns t avqv t acc address valid to output valid max 70 85 90 100 ns t axqx (1) t oh address transition to output transition min 0 0 0 0 ns t ehqx (1) t oh chip enable high to output transition min 0 0 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 20 20 25 30 ns t elqv (2) t ce chip enable low to output valid max 70 85 90 100 ns t elqx (1) t lz chip enable low to output transition min 0 0 0 0 ns t ghqx (1) t oh output enable high to output transition min 0 0 0 0 ns t ghqz (1) t df output enable high to output hi-z max 20 20 25 30 ns t glqv (2) t oe output enable low to output valid max 20 20 30 35 ns t glqx (1) t olz output enable low to output transition min 0 0 0 0 ns 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv .
dc and ac parameters m28w320fct, m28w320fcb 36/69 figure 9. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid a0-a20 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai03574b twphwh wp twhgl tqvwpl twhel
m28w320fct, m28w320fcb dc and ac parameters 37/69 table 17. write ac characteristics, write enable controlled symbol alt parameter m28w320fct, m28w320fcb unit 70 85 90 10 t avav t wc write cycle time min 70 85 90 100 ns t avwh t as address valid to write enable high min 45 45 50 50 ns t dvwh t ds data valid to write enable high min 45 45 50 50 ns t elwl t cs chip enable low to write enable low min 0 0 0 0 ns t elqv chip enable low to output valid min 70 85 90 100 ns t qvvpl (1)(2) output valid to v pp low min 0 0 0 0 ns t qvwpl output valid to write protect low min 0 0 0 0 ns t vphwh (1) t vps v pp high to write enable high min 200 200 200 200 ns t whax t ah write enable high to address transition min 0 0 0 0 ns t whdx t dh write enable high to data transition min 0 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 0 ns t whel write enable high to chip enable low min 25 25 30 30 ns t whgl write enable high to output enable low min 20 20 30 30 ns t whwl t wph write enable high to write enable low min 25 25 30 30 ns t wlwh t wp write enable low to write enable high min 45 45 50 50 ns t wphwh write protect high to write enable high min 45 45 50 50 ns 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v).
dc and ac parameters m28w320fct, m28w320fcb 38/69 figure 10. write ac waveforms, chip enable controlled e g dq0-dq15 command cmd or data status register v pp valid a0-a20 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling telqv ai03575b w twpheh wp tehgl tqvwpl
m28w320fct, m28w320fcb dc and ac parameters 39/69 table 18. write ac characteristics, chip enable controlled symbol alt parameter m28w320fct, m28w320fcb unit 70 85 90 10 t avav t wc write cycle time min 70 85 90 100 ns t aveh t as address valid to chip enable high min 45 45 50 50 ns t dveh t ds data valid to chip enable high min 45 45 50 50 ns t ehax t ah chip enable high to address transition min 0 0 0 0 ns t ehdx t dh chip enable high to data transition min 0 0 0 0 ns t ehel t cph chip enable high to chip enable low min 25 25 30 30 ns t ehgl chip enable high to output enable low min 25 25 30 30 ns t ehwh t wh chip enable high to write enable high min 0 0 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 50 50 ns t elqv chip enable low to output valid min 70 85 90 100 ns t qvvpl (1) (2) output valid to v pp low min 0 0 0 0 ns t qvwpl data valid to write protect low min 0 0 0 0 ns t vpheh (1) t vps v pp high to chip enable high min 200 200 200 200 ns t wlel t cs write enable low to chip enable low min 0 0 0 0 ns t wpheh write protect high to chip enable high min 45 45 50 50 ns 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v).
dc and ac parameters m28w320fct, m28w320fcb 40/69 figure 11. power-up and reset ac waveforms ai03537b w, rp tphwl tphel tphgl e, g vdd, vddq tvdhph tphwl tphel tphgl tplph power-up reset table 19. power-up and reset ac characteristics symbol parameter test condition m28w320fct, m28w320fcb unit 70 85 90 10 t phwl t phel t phgl reset high to write enable low, chip enable low, output enable low during program and erase min50505050s others min 30 30 30 30 ns t plph (1)(2) reset low to reset high min 100 100 100 100 ns t vdhph (3) supply voltages high to reset high min 50 50 50 50 s 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power up or reset.
m28w320fct, m28w320fcb package mechanical 41/69 9 package mechanical figure 12. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline 1. drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 table 20. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 ? ? 0.0197 ? ? l 0.50 0.70 0.0197 0.0279 0 5 0 5 n48 48 cp 0.10 0.0039
package mechanical m28w320fct, m28w320fcb 42/69 figure 13. tfbga47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, bottom view package outline 1. drawing is not to scale. e1 e d1 d b a2 a1 a bga-z35 ddd e e fd fe sd se ball "a1" table 21. tfbga47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.390 6.290 6.490 0.2516 0.2476 0.2555 d1 5.250 ? ? 0.2067 ? ? ddd 0.100 0.0039 e 6.370 6.270 6.470 0.2508 0.2469 0.2547 e1 3.750 ? ? 0.1476 ? ? e 0.750 ? ? 0.0295 ? ? fd 0.570 ? ? 0.0224 ? ? fe 1.310 ? ? 0.0516 ? ? sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ?
m28w320fct, m28w320fcb package mechanical 43/69 figure 14. tfbga47 daisy chain - package connections (top view through package) figure 15. tfbga47 daisy chain - pcb connections proposal (top view through package) ai03295 c b a 8 7 6 5 4 3 2 1 e d f ai03296 c b a 8 7 6 5 4 3 2 1 e d f start point end point
part numbering m28w320fct, m28w320fcb 44/69 10 part numbering table 22. ordering information scheme example: m28w320fct 70 n 6 e device type m28 operating voltage w = v dd = 2.7v to 3.6v; v ddq = 1.65v to 3.6v device function 320fc = 32 mbit (2 mb x16), boot block array matrix t = top boot b = bottom boot speed 70 = 70ns 85 = 85ns 90 = 90ns 10 = 100ns package n = tsop48: 12 x 20mm zb = tfbga47: 6.39 x 6.37mm, 0.75 mm pitch temperature range 6 = ?40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape & reel 24mm packing
m28w320fct, m28w320fcb part numbering 45/69 devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 23. daisy chain ordering scheme example:m28w320fc -zb e device type m28w320fc daisy chain -zb = tfbga47: 6.39 x 6.37mm, 0.75 mm pitch option e = ecopack package, standard packing f = ecopack package, tape & reel 24mm packing
block address tables m28w320fct, m28w320fcb 46/69 appendix a block address tables table 24. top boot block addresses, m28w320fct # size (kword) address range 0 4 1ff000-1fffff 1 4 1fe000-1fefff 2 4 1fd000-1fdfff 3 4 1fc000-1fcfff 4 4 1fb000-1fbfff 5 4 1fa000-1fafff 6 4 1f9000-1f9fff 7 4 1f8000-1f8fff 8 32 1f0000-1f7fff 9 32 1e8000-1effff 10 32 1e0000-1e7fff 11 32 1d8000-1dffff 12 32 1d0000-1d7fff 13 32 1c8000-1cffff 14 32 1c0000-1c7fff 15 32 1b8000-1bffff 16 32 1b0000-1b7fff 17 32 1a8000-1affff 18 32 1a0000-1a7fff 19 32 198000-19ffff 20 32 190000-197fff 21 32 188000-18ffff 22 32 180000-187fff 23 32 178000-17ffff 24 32 170000-177fff 25 32 168000-16ffff 26 32 160000-167fff 27 32 158000-15ffff 28 32 150000-157fff 29 32 148000-14ffff 30 32 140000-147fff 31 32 138000-13ffff
m28w320fct, m28w320fcb block address tables 47/69 32 32 130000-137fff 33 32 128000-12ffff 34 32 120000-127fff 35 32 118000-11ffff 36 32 110000-117fff 37 32 108000-10ffff 38 32 100000-107fff 39 32 0f8000-0fffff 40 32 0f00000-f7fff 41 32 0e8000-0effff 42 32 0e0000-0e7fff 43 32 0d8000-0dffff 44 32 0d0000-0d7fff 45 32 0c8000-0cffff 46 32 0c0000-0c7fff 47 32 0b8000-0bffff 48 32 0b0000-0b7fff 49 32 0a8000-0affff 50 32 0a0000-0a7fff 51 32 098000-09ffff 52 32 090000-097fff 53 32 088000-08ffff 54 32 080000-087fff 55 32 078000-07ffff 56 32 070000-077fff 57 32 068000-06ffff 58 32 060000-067fff 59 32 058000-05ffff 60 32 050000-057fff 61 32 048000-04ffff 62 32 040000-047fff 63 32 038000-03ffff 64 32 030000-037fff 65 32 028000-02ffff 66 32 020000-027fff table 24. top boot block addresses, m28w320fct (continued) # size (kword) address range
block address tables m28w320fct, m28w320fcb 48/69 67 32 018000-01ffff 68 32 010000-017fff 69 32 008000-00ffff table 25. bottom boot block addresses, m28w320fcb # size (kword) address range 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff table 24. top boot block addresses, m28w320fct (continued) # size (kword) address range
m28w320fct, m28w320fcb block address tables 49/69 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff table 25. bottom boot block addresses, m28w320fcb (continued) # size (kword) address range
block address tables m28w320fct, m28w320fcb 50/69 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff table 25. bottom boot block addresses, m28w320fcb (continued) # size (kword) address range
m28w320fct, m28w320fcb common flash interface (cfi) 51/69 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. ta bl e 2 6 , ta b l e 2 7 , ta b l e 2 8 , ta bl e 2 9 , ta bl e 3 0 and ta bl e 3 1 show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is written (see table 31: security code area ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. issue a read command to return to read mode. table 26. query structure overview (1) offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 1. query data are always presented on the lowest order data outputs. table 27. cfi query identification string (1) offset data description value 00h 0020h manufacturer code numonyx 01h 88bah 88bbh device code to p bottom 02h-0fh reserved reserved 10h 0051h "q" 11h 0052h query unique ascii string "qry" "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm intel compatible 14h 0000h 15h 0035h address for primary algorithm extended query table (see ta bl e 2 9 ) p = 35h 16h 0000h
common flash interface (cfi) m28w320fct, m28w320fcb 52/69 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (0000h means none exists) na 18h 0000h 19h 0000h address for alternate algorithm extended query table (0000h means none exists) na 1ah 0000h 1. query data are always presented on the lowest or der data outputs (dq7-dq0) only. dq8-dq15 are ?0?. table 27. cfi query identification string (1) (continued) offset data description value table 28. cfi query system interface information offset data description value 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 2.7v 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 3.6v 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 11.4v 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12.6v 1fh 0004h typical time-out per single word program = 2 n s 16s 20h 0004h typical time-out for double/ quadruple word program = 2 n s 16s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0005h maximum time-out for word program = 2 n times typical 512s 24h 0005h maximum time-out for double/ quadruple word program = 2 n times typical 512s 25h 0003h maximum time-out per individual block erase = 2 n times typical 8s 26h 0000h maximum time-out for chip erase = 2 n times typical na
m28w320fct, m28w320fcb common flash interface (cfi) 53/69 table 29. device geometry definition offset word mode data description value 27h 0016h device size = 2 n in number of bytes 4 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 2ch 0002h number of erase block regions within the device. it specifies the number of regions wi thin the device containing contiguous erase blocks of the same size. 2 m28w320fct 2dh 2eh 003eh 0000h region 1 information number of identical-size erase block = 003eh+1 63 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase block = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte m28w320fcb 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 003eh 0000h region 2 information number of identical-size erase block = 003eh=1 63 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte
common flash interface (cfi) m28w320fct, m28w320fcb 54/69 table 30. primary algorithm-specific extended query table offset p = 35h (1) data description value (p+0)h = 35h 0050h primary algorithm extended query table unique ascii string ?pri? "p" (p+1)h = 36h 0052h "r" (p+2)h = 37h 0049h "i" (p+3)h = 38h 0031h major version number, ascii "1" (p+4)h = 39h 0030h minor version number, ascii "0" (p+5)h = 3ah 0066h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0chip erase supported(1 = yes, 0 = no) bit 1suspend erase supported(1 = yes, 0 = no) bit 2suspend program supported(1 = yes, 0 = no) bit 3legacy lock/unlock supported(1 = yes, 0 = no) bit 4queued erase supported(1 = yes, 0 = no) bit 5instant individual block locking supported(1 = yes, 0 = no) bit 6protection bits supported(1 = yes, 0 = no) bit 7page mode read supported(1 = yes, 0 = no) bit 8synchronous read supported(1 = yes, 0 = no) bit 31 to 9reserved; undefined bits are ?0? no ye s ye s no no ye s ye s no no (p+6)h = 3bh 0000h (p+7)h = 3ch 0000h (p+8)h = 3dh 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1reserved; undefined bits are ?0? ye s (p+a)h = 3fh 0003h block lock status defines which bits in the block status register section of the query are implemented. address (p+a)h contains less significant byte bit 0block lock status register lock/ unlock bit active(1 = yes, 0 = no) bit 1block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2reserved for future use; undefined bits are ?0? ye s ye s (p+b)h = 40h 0000h (p+c)h = 41h 0030h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 3v (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12v (p+e)h = 43h 0001h number of protection register fields in jedec id space. "00h," indicates that 256 protection bytes are available 01
m28w320fct, m28w320fcb common flash interface (cfi) 55/69 (p+f)h = 44h 0080h protection field 1: protection description this field describes user-available. one time programmable (otp) protection register bytes. some are pre-programmed with device unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock by te, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bit 0 to 7 lock/bytes jedec-plane physical low address bit 8 to 15lock/bytes jedec-plane physical high address bit 16 to 23 "n" such that 2 n = factory pre-programmed bytes bit 24 to 31 "n" such that 2 n = user programmable bytes 80h (p+10)h = 45h 0000h 00h (p+11)h = 46h 0003h 8 byte (p+12)h = 47h 0003h 8 byte (p+13)h = 48h reserved 1. see ta bl e 2 7 , offset 15 for p pointer definition. table 30. primary algorithm-specific extended query table offset p = 35h (1) data description value table 31. security code area offset data description 80h 00xx protection register lock 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx 85h xxxx 128 bits: user programmable otp 86h xxxx 87h xxxx 88h xxxx 89h xxxx 8ah xxxx 8bh xxxx 8ch xxxx
flowcharts and pseudo codes m28w320fct, m28w320fcb 56/69 appendix c flowcharts and pseudo codes figure 16. program flowchart and pseudo code 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) c an be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. write 40h or 10h ai03538b start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0x40) ; /*or writetoflash (any_address, 0x10) ; */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
m28w320fct, m28w320fcb flowcharts and pseudo codes 57/69 figure 17. double word program flowchart and pseudo code 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) c an be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 mu st be consecutive addresses differing only for bit a0. write 30h ai03539b start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (any_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudo codes m28w320fct, m28w320fcb 58/69 figure 18. quadruple word program flowchart and pseudo code 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) c an be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differi ng only for bits a0 and a1. write 56h ai06233 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (any_address, 0x56) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
m28w320fct, m28w320fcb flowcharts and pseudo codes 59/69 figure 19. program suspend & resume flowchart and pseudo code write 70h ai03540b read status register yes no b7 = 1 yes no b2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b2==0) /*program completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
flowcharts and pseudo codes m28w320fct, m28w320fcb 60/69 figure 20. erase flowchart and pseudo code 1. if an error is found, the status register must be cleared before further program/erase operations. write 20h ai03541b start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1 v pp invalid error (1) command sequence error (1) no no b5 = 0 erase error (1) end yes no b1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (any_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.b7== 0) ; do { status_register=readflash (any_address) ; /* e or g must be toggled*/ if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; }
m28w320fct, m28w320fcb flowcharts and pseudo codes 61/69 figure 21. erase suspend & resume flowchart and pseudo code write 70h ai03542b read status register yes no b7 = 1 yes no b6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b6==0) /*erase completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
flowcharts and pseudo codes m28w320fct, m28w320fcb 62/69 figure 22. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai04364 read block lock states yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (any_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (any_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (any_address, 0x90) ;
m28w320fct, m28w320fcb flowcharts and pseudo codes 63/69 figure 23. protection register program flowchart and pseudo code 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) c an be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. write c0h ai04381 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0xc0) ; do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
command interface and program/erase controller state m28w320fct, m28w320fcb 64/69 appendix d command interface and program/erase controller state table 32. write state machine current/next, sheet 1 of 2. (1) current state sr bit 7 data when read command input (and next state) read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read array ?1? array read array prog. setup ers. setup read array read sts. read array read status ?1? status read array program setup erase setup read array read sts read array read elect.sg. ?1? electronic signature read array program setup erase setup read array read sts read array read cfi query ?1? cfi read array program setup erase setup read array read sts read array lock setup ?1? status lock command error lock (complete) lock cmd error lock (complete) lock command error lock cmd error ?1? status read array program setup erase setup read array read sts read array lock (complete) ?1? status read array program setup erase setup read array read sts read array prot. prog. setup ?1? status protection register program prot. prog. (continue) ?0? status protection register program continue prot. prog. (complete) ?1? status read array program setup erase setup read array read sts read array prog. setup ?1? status program program (continue) ?0? status program (continue) prog. sus read sts program (continue) prog. sus status ?1? status prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read array ?1? array prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read elect.sg. ?1? electronic signature prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read cfi ?1? cfi prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array program (complete) ?1? status read array program setup erase setup read array read sts read array
m28w320fct, m28w320fcb command interface and program/erase controller state 65/69 erase setup ?1? status erase command error erase (continue) erase cmderror erase (continue) erase command error erase cmd.error ?1? status read array program setup erase setup read array read sts read array erase (continue) ?0? status erase (continue) erase sus read sts erase (continue) erase sus read sts ?1? status erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read array ?1? array erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read elect.sg. ?1? electronic signature erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read cfi ?1? cfi erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase (complete) ?1? status read array program setup erase setup read array read sts read array 1. cmd = command, elect.sg. = electronic signature, ers = er ase, prog. = program, prot = protection, sus = suspend. table 32. write state machine current/next, sheet 1 of 2. (1) (continued) current state sr bit 7 data when read command input (and next state) read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h)
command interface and program/erase controller state m28w320fct, m28w320fcb 66/69 table 33. write state machine current/next, sheet 2 of 2 (1) current state command input (and next state) read elect.sg. (90h) read cfi query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read elect.sg. read cfi query lock setup prot. prog. setup read array read status read elect.sg. read cfi query lock setup prot. prog. setup read array read elect.sg. read elect.sg. read cfi query lock setup prot. prog. setup read array read cfi query read elect.sg. read cfi query lock setup prot. prog. setup read array lock setup lock command error lock (complete) lock cmd error read elect.sg. read cfi query lock setup prot. prog. setup read array lock (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (continue) protection register program (continue) prot. prog. (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prog. setup program program (continue) program (continue) prog. suspend read status prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read array prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read elect.sg. prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read cfi prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) program (complete) read elect.sg. read cfiquery lock setup prot. prog. setup read array erase setup erase command error erase (continue) erase cmd.error read elect.sg. read cfi query lock setup prot. prog. setup read array
m28w320fct, m28w320fcb command interface and program/erase controller state 67/69 erase (continue) erase (continue) erase suspend read ststus erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read array erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read elect.sg. erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read cfi query erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array 1. cmd = command, elect.sg. = electronic signat ure, prog. = program, prot = protection. table 33. write state machine current/next, sheet 2 of 2 (continued) (1) current state command input (and next state) read elect.sg. (90h) read cfi query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h)
revision history m28w320fct, m28w320fcb 68/69 11 revision history table 34. document revision history date revision changes 24-may-2004 0.1 first issue 23-aug-2004 0.2 figure 2: tsop connections and figure 3: tfbga connections (top view through package) . 12-jul-2005 1.0 datasheet status promoted to full datasheet. 85, 90 and 100ns speed classes removed. temperature range 1 (0 to 70c) removed. leaded package options removed and ecopack text updated. 28-mar-2006 2 85, 90 and 100ns access time added. table 13: operating and ac measurement conditions , ta bl e 1 6 : read ac characteristics , table 17: write ac characteristics, write enable controlled , table 18: write ac characteristics, chip enable controlled , and table 19: power-up and reset ac characteristics updated. table 22: ordering information scheme modified. 16-oct-2006 3 device function updated in table 22: ordering information scheme to remove the 0.13m technology. 10-dec-2007 4 applied numonyx branding.
m28w320fct, m28w320fcb 69/69 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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